The present invention relates to a demodulator circuit of quadrature amplitude modulation (QAM) signals, and in particular, to a digital demodulator for producing a digital demodulation signal through digital signal processing by an analog-to-digital converter.
Heretofore, the quadrature amplitude modulation method has been broadly employed in various fields because of its capability of highly efficient data transmission in a limited transmission frequency band. In relation to applications thereof, there has been used a demodulator to generate digital data in a circuit configuration in which a received signal is quadrature-demodulated to be thereafter converted into a digital signal.
An example of the demodulator in which an analog signal is directly demodulated such that the demodulated signal is converted into a digital signal has been described in pages 115 and 116 of "Signal Modulation and Demodulation for Digital Radio Communication" written by Yoichi Saito and published from the Institute of Electronics, Information and Communication Engineers (IEIC) on Aug. 20, 1996. Referring to FIG. 2, the demodulator circuit will be described.
In the demodulator shown in FIG. 2, a signal to be demodulated, i.e., a signal generated through a quadrature amplitude demodulation with a predetermined carrier frequency and a predetermined bandwidth is received by a front-end section of a receiver, not shown. The received radio frequency (RF) signal is converted into a signal of an intermediate carrier frequency f.sub.IF of, e.g., 450 kHz. The signal is then amplified by an intermediate-frequency amplifier section according to a predetermined gain to be supplied to an input terminal 1.
The received signal fed to the input terminal 1 is limited to a predetermined band through a band-pass filter 2 and then is inputted to multipliers 3i and 3q.
On the other hand, an oscillator 4 generates a signal having the frequency of the intermediate frequency (IF) signal, i.e., 450 kHz. The obtained signal is directly fed to the multiplier 3i and is supplied via a 90-degree phase shifter 5 to the multiplier 3q. These signals are each multiplied by the received signal to thereby conduct a quadrature demodulation to produce an in-phase (I) signal component and a quadrature-phase (Q) signal component.
Subsequently, the I and Q signal components synchronously demodulated by the multipliers 3i and 3q are respectively fed to low-pass filters 6i and 6q such that unnecessary harmonic components are removed therefrom. The signals passed through the filters 6i and 6q are then digitized respectively by analog-to-digital (A/D) converters 7i and 7q at a conversion rate (with a sampling frequency fs) of, e.g., 100 kHz to be converted into a digitized I signal and a digitized Q signal, respectively.
The I and Q signals in the digital form are inputted respectively to digital low-pass filters 8i and 8q such that a waveform shaping operation and a sampling frequency conversion are accomplished for the signals to resultantly obtain digital outputs, i.e., digital demodulated signals.
For the demodulator of the analog signal processing shown in FIG. 2, an initial adjustment is required after the demodulator is manufactured. Moreover, consideration has not been given to a phenomenon that characteristics of the demodulator inevitably change in relation to change in the operating conditions thereof, which leads to a problem of difficulty in the improvement of stability and precision.
That is, since the quadrature demodulation is accomplished through analog processing, there inevitably appear influences from, for example, constituent components of the analog circuit such as the precision with respect to phase of the 90-degree phase shifter, the frequency deviation or shift of the low-pass filter, and/or the phase amplitude error of the analog-to-digital (A/D) converter.
In consequence, there is required the initial adjustment for the characteristics above. Moreover, the characteristic are inevitably varied due to the change in temperature and power supply voltage as well as with lapse of time and hence the improvement of stability and precision is associated with difficulties.
In addition to the digital demodulator conducting the A/D conversion for the signal undergone the analog processing, there has been already known a digital demodulator of a circuit configuration in which the signal demodulation is carried out through digital signal processing.
An example of the demodulator to conduct the demodulation through digital signal processing has been described in page 171 of "Application of Digital Signal Processing" written by Nobuo Inoue and published from IEIC on Jul. 10, 1983.
According to the operation method of the digital signal processing circuit described above, the problem of the demodulation through the analog processing above can be avoided. However, in the method employing the digital signal circuit, there is required as a sampling frequency for the A/D conversion a frequency corresponding to the carrier frequency of the signal to be demodulated. As a result, this requires circuit elements operating at a high speed. Moreover, for the quadrature demodulator circuit and the digital low-pass filter, there are required complex signal generator circuits, multipliers, high-speed digital filter large-scale integrated circuits, which disadvantageously leads to increase in the circuit size.
Additionally, there can be considered a method in which the frequency of the signal to be demodulated is shifted to a base band before the digital demodulation. However, the circuit configuration becomes also complicated also in this case.